FIG. 1A shows a resonant half-bridge inverter which includes, in addition to a resonant circuit, a primary supply 4 of direct voltage V.sub.DD, a coupling transformer T.sub.1 with a primary winding and split-phase secondary windings, switching transistors Q.sub.1 and Q.sub.2, clamp diodes D.sub.1 and D.sub.2, and charge capacitors C.sub.1, C.sub.2, C.sub.3 and C.sub.4. The resonant circuit is formed from the series connection of a resonance inductor L.sub.r with a parallel connection of a resonance capacitor C.sub.r and a load resistance R.sub.L. The resonant inverter is useful for high-frequency lighting using a fluorescent light or a discharge lamp, for example, with the fluorescent light or discharge lamp providing the load resistance R.sub.L and some portion of the resonance capacitor C.sub.r. In such instances, the load resistance R.sub.L exhibits substantial variation caused by changing conditions in the conduction through plasma, and the resonance inductor L.sub.r provides ballasting. The primary supply 4 may be a battery of electrochemical cells, as when a fluorescent light or discharge lamp is used in emergency lighting. Alternatively, the primary supply 4 may instead comprise a rectifier for rectifying alternating voltage and a smoothing filter for converting the rectified alternating voltage to direct voltage. Such arrangement is useful, for example, for converting 60-cycle power from the electric mains to higher frequency to avoid flicker in lighting using a fluorescent light or a discharge lamp.
A switching signal appearing between terminals OUT1 and OUT2 applied to the primary winding of the transformer T.sub.1 comprises, in effect, pulses that are alternately positive and negative in polarity. Respective secondary windings of the transformer T.sub.1 apply this switching signal between the source and gate electrodes of the switching transistors Q.sub.1, and Q.sub.2, respectively, for conditioning them for alternate drain-to-source conduction with intervening intervals that neither of them is conditioned for drain-to-source conduction. The beginning of each interval when one of the switching transistors Q.sub.1 and Q.sub.2 is conditioned for drain-to-source conduction is timed to precede a zero-current condition in the resonance inductor L.sub.r. This is so that the switching transistor comes into conduction immediately upon reversal of the polarity of its source-to-drain potential as the resonant current flowing through the resonance inductor L.sub.r builds up in polarity opposite to its previous polarity.
The capacitors C.sub.1 and C.sub.2 function primarily as commutating capacitors, and normally their respective capacitances are designed to be the same as each other. The capacitors C.sub.1 and C.sub.2 are made not to be too large in capacitance, so that losses owing to dissipation of their charge in the switching devices should switching be mis-timed does not reduce conversion efficiency of the resonant inverter too much. Normally, the respective capacitances of the capacitors C.sub.3 and C.sub.4 are designed to be the same as each other, as well, so that after operation is established in the resonant half-bridge inverter, the quiescent voltage at the interconnection of the charge capacitors C.sub.3 and C.sub.4 is essentially V.sub.DD /2as referred to the negative terminal of the V.sub.DD direct voltage supply 4. Furthermore, the capacitances of the charge capacitors C.sub.3 and C.sub.4 are customarily made large enough to suppress reasonably well the ripple voltage at their interconnection. The primary supply 4 is designed to include sufficient internal resistance that the initial charging of the capacitors C.sub.1, C.sub.2, C.sub.3 and C.sub.4 proceeds slowly enough that charging currents are not excessive.
The drain-to-source conduction of the switching transistor Q.sub.1 maintains the capacitor C.sub.1 discharged, applies a voltage that builds up the field surrounding the winding of the inductor L.sub.r to cause an increasing positive current i.sub.L flow therethrough, and charges the capacitor C.sub.2 until the direct voltage supply potential V.sub.DD appears between its plates. The positive current i.sub.L flows from the positive terminal of the primary supply 4 through the conductive channel of the transistor Q.sub.1 (which channel is the principal conduction path of that transistor), through the inductor L.sub.r, through the parallel connection of the resonant capacitor C.sub.r and the load resistor R.sub.L and returns to the negative terminal of the primary supply 4 via capacitor C.sub.2. When the capacitor C.sub.2 charges so the direct voltage supply potential V.sub.DD appears between its plates, drain-to-source conduction of the switching transistor Q.sub.1 halts owing to lack of drain-to-source potential. The trailing edge of the positive pulse in the switching signal that conditions the switching transistor Q.sub.1 to exhibit drain-to-source conduction is caused to occur at this time. The field surrounding the winding of the inductor L.sub.r begins to collapse, tending to maintain the demand for positive current i.sub.L flowing through the inductor L.sub.r in accordance with Lenz's Law, discharging the capacitor C.sub.2 and charging the capacitor C.sub.1 as the voltage V.sub.g at the node between the capacitors C.sub.1 and C.sub.2 falls during to a ground potential at the negative terminal of the direct voltage supply 4. The field surrounding the winding of the inductor L.sub.r continues to collapse, tending to maintain the demand for positive current i.sub.L flowing through the inductor L.sub.r in accordance with Lenz's Law, and the clamp diode D.sub.2 for the switching transistor Q.sub.1 is drawn into conduction until the field surrounding the winding of the inductor L.sub.r is completely collapsed and the demand for positive current i.sub.L ceases. When the demand for positive current i.sub.L ceases, the cathode of the diode D.sub.2 is no longer pulled negative respective to its anode. The leading edge of the negative pulse in the switching signal that conditions the switching transistor Q.sub.2 to exhibit drain-to-source conduction preferably occurs after the redistribution of charge from the capacitor C.sub.2 to the capacitor C.sub.1 and before free-running in the resonant circuit formed by the inductor L.sub.r and the capacitor C.sub.r begins to demand negative current i.sub.L.
The drain-to-source conduction of the switching transistor Q.sub.2 maintains the capacitor C.sub.2 discharged, applies a voltage that builds up the field surrounding the winding of the inductor L.sub.r to cause an increasing negative current i.sub.L flow therethrough, and charges the capacitor C.sub.1 until the direct voltage supply V.sub.DD potential appears between its plates. The negative current i.sub.L flows to the negative terminal of the primary supply 4 through the conductive channel of the transistor Q.sub.2 (which channel is the principal conduction path of that transistor) from the inductor L.sub.r being drawn from the positive terminal of the primary supply 4 to the inductor L.sub.r via the capacitor C.sub.3 and thence the parallel connection of the resonant capacitor C.sub.1 and the load resistor R.sub.L. When the capacitor C.sub.2 charges so the direct voltage supply potential V.sub.DD appears between its plates, halts owing to lack of drain-to-source potential. The trailing edge of the negative pulse in the switching signal that conditions the switching transistor Q.sub.2 to exhibit drain-to-source conduction is caused to occur at this time. The field surrounding the winding of the inductor L.sub.r begins to collapse, tending to maintain the demand for negative current i.sub.L flowing through the inductor L.sub.r in accordance with Lenz's Law, discharging the capacitor C.sub.1 and charging the capacitor C.sub.2 as the voltage V.sub.g at the node between the capacitors C.sub.1 and C.sub.2 rises during flyback to the V.sub.DD potential at the positive terminal of the direct voltage supply 4. The field surrounding the winding of the inductor L.sub.r continues to collapse, tending to maintain the demand for positive current i.sub.L flowing through the inductor L.sub.r in accordance with Lenz's Law, and the clamp diode D.sub.1 is driven into conduction until the field surrounding the winding of the inductor L.sub.r is completely collapsed and the demand for negative current i.sub.L ceases. When the demand for negative current i.sub.L ceases, the anode of the diode D.sub.1 is no longer pushed positive respective to its cathode. The leading edge of the positive pulse in the switching signal that conditions the switching transistor Q.sub.1 to exhibit drain-to-source conduction preferably occurs after the redistribution of charge from the capacitor C.sub.1 to the capacitor C.sub.2 and before free-running in the resonant circuit formed by the inductor L.sub.R and the capacitor C.sub.r begins to demand positive current i.sub.L.
FIG. 1B shows the waveform of the current i.sub.L flowing through the inductor L.sub.R Of the FIG. 1A circuit during the cycle when the switching transistors Q.sub.1 and Q.sub.2 are alternately conditioned to exhibit drain-to-source conduction. In FIG. 1B the time t.sub.0 is that at which the switching transistor Q.sub.1 is conditioned by switching signal applied between its source and gate electrodes to exhibit drain-to-source conduction. The time t.sub.1 is that at which the switching transistor Q.sub.1 quits conduction. The charge interval for capacitor C.sub.1 and the discharge interval for capacitor C.sub.2 extend for the time duration t.sub.d1 from time t.sub.1 until time t.sub.2, and the interval when the diode D.sub.2 is drawn into conduction extends for the time duration t.sub.d2 from time t.sub.2 until time t.sub.3. The switching signal applied between the source and gate electrodes of the switching transistor Q.sub.2 should begin to condition transistor Q.sub.2 to exhibit drain-to-source conduction some time after time t.sub.2, but no later than time t.sub.3.
Applying the switching signal between the source and gate electrodes of the switching transistor Q.sub.2 before time t.sub.2 conditions the transistor for inverse-mode conduction before the charging of the capacitor C.sub.1 and the discharging of the capacitor C.sub.2 are completed so the source-to-drain voltage of transistor Q.sub.2 is essentially zero before it is conditioned for conduction. Charge remaining in capacitor C.sub.2 has to be dissipated by conduction through the switching transistor Q.sub.2, and the charging of the capacitor C.sub.1 has to be completed by drawing current from the primary supply 4 through the conductive switching transistor Q.sub.2. This switching loss, and analogous switching loss when the switching transistor Q.sub.1 is conditioned for drain-to-source conduction too early, undesirably reduces conversion efficiency.
In practice, the switching signal applied between the source and gate electrodes of the switching transistor Q.sub.2 generally has to be applied somewhat earlier than time t.sub.3, while the source-to-drain voltage of transistor Q.sub.2 is essentially zero. Otherwise, capacitor C.sub.1 is discharged somewhat, so its charging must be completed by drawing current from the primary supply 4 through the conductive switching transistor Q.sub.2 ; and charge undesirably builds up in capacitor C.sub.2 that has to be dissipated by conduction through the switching transistor Q.sub.2. This switching loss, and analogous switching loss when the switching transistor Q.sub.1 is conditioned for drain-to-source conduction too late, also undesirably reduces conversion efficiency. Undesirable glitches are introduced into the waveform of the voltage V.sub.g as well.
In the prior art the timings of the leading edges of the pulses in the switching signal applied across the primary winding of the split-phase coupling transformer T.sub.1 have been inferred from the trailing edges of the immediately preceding pulses. However, the method has a practical problem that the timing of the occurrence of the zero-current condition in the resonant inductor L.sub.r, as referred to the switching off of the switching transistors, varies. Variation is caused by changes in the voltage V.sub.DD supplied by the direct voltage supply 4 and by changes in the loading on the resonant circuit, which alter the decay time of the resonant current. Accordingly, the leading edges of the switching signal that condition the switching transistors to exhibit drain-to-source conduction have to be timed to be early enough to suit the worst-case increases in the voltage V.sub.DD and the worst-case heaviest loading on the resonant circuit in order to prevent the introduction of undesirable glitches into the waveform of the voltage V.sub.g. The timing of the completion of charge redistribution in the capacitors C.sub.1 and C.sub.2 is also affected by changes in the voltage V.sub.DD supplied by the direct voltage supply 4 and by changes in the loading on the resonant circuit, however, so the design should try to avoid the possibility of undesirable switching loss owing to the leading edges of the switching signal being made too early during worst-case decreases in the voltage V.sub.DD and the worst-case reductions in loading on the resonant circuit.
There is a desire, then, for a better way to time the leading edges of the switching signal applied to the switching transistors Q.sub.1 and Q.sub.2 to assure that they occur during the periods of forward conduction by the diodes D.sub.1 and D.sub.2. Preferably, this better way is one that does not require additional coupling transformers.
In the resonant inverter of FIG. 1 the source-to-drain voltage of the switching transistor Q.sub.1 is close to being zero-valued when the clamp diode D.sub.1 conducts and becomes zero-valued at the time the diode D.sub.1 stops conducting responsive to the resonant current I.sub.L passing through zero value to become positive in polarity. Conditioning the switching transistor Q.sub.1 for conduction when its source-to-drain voltage is close to being zero-valued means that the capacitor C.sub.1 in parallel with its channel is substantially discharged and conduction through the channel of transistor Q.sub.1 does not dissipate substantial stored charge from the capacitor C.sub.1 causing energy losses that must subsequently be replenished by drawing energy from the primary supply 4. Sensing when there is forward conduction by the diode D.sub.1 provides an indication that the source-to-drain voltage of the transistor Q.sub.1 is close to being zero-valued. Similarly, the source-to-drain voltage of the switching transistor Q.sub.2 is close to being zero-valued when the clamp diode D.sub.2 conducts and becomes zero-valued at the time the diode D.sub.2 stops conducting responsive to the resonant current I.sub.L passing through zero value to become negative in polarity. Conditioning the switching transistor Q.sub.2 for conduction when its source-to-drain voltage is close to being zero-valued means that the capacitor C.sub.2 in parallel with its channel is substantially discharged and conduction through the channel of transistor Q.sub.2 does not dissipate substantial stored charge from the capacitor C.sub.2 causing energy losses that must subsequently be replenished by drawing energy from the primary supply 4. Sensing when there is forward conduction by the diode D.sub.2 provides an indication that the source-to-drain voltage of the transistor Q.sub.2 is close to being zero-valued. The current flow to or from either of the terminals of the primary direct voltage supply 4 is in a first direction when either of the switching transistors is conductive and is in a second direction opposite to the first direction when either of the clamp diodes is conductive. The observations in this paragraph, the inventors point out, form the basis for being able to control the leading edges of the pulses in the switching signal so that they occur when the source-to-drain voltage of the one of the switching transistors Q.sub.1 and Q.sub.2 being switched into conduction is substantially zero-valued.
The flow of current through the clamp diodes of a resonant inverter can be sensed without need for a further coupling transformer, the inventors point out, even though one (or both) of the switching transistors has its source electrode connected other than to one of the terminals of the primary direct voltage supply 4. The current flow to or from either of the terminals of the primary direct voltage supply 4, which current flow is in a first direction when either of the switching transistors is conductive and to the extent it exists when the clamp diodes are conductive is in a second direction opposite to the first direction, is sensed for determining the times when the switching transistors are to begin to be conditioned for conduction. The switching transistors begin to be conditioned for conduction when the current flow is in the second direction.